1. Field of the Invention
The present invention relates to a semiconductor device, specifically to a semiconductor device that includes a planarized electrode of transistors and a larger area of safety operation (ASO), and that is capable of avoiding thermal runaway, and of decreasing resistance components.
2. Description of the Related Art
As a discrete bipolar transistor, there has been known a bipolar transistor having a base electrode and an emitter electrode each formed in two layers on an operation region including an emitter region formed in a lattice form and base regions formed in islands. This technology is described for instance in Japanese Patent Application Publication No. 2000-40703.
With reference to FIG. 6, a conventional semiconductor device will be described taking npn type transistors as an example.
FIG. 6A is a plan view of an entire semiconductor device 100. FIG. 6B is a cross-sectional view taken along the line j-j in FIG. 6A, and FIG. 6C is a cross-sectional view taken along the line k-k in FIG. 6A. Note that the broken lines in FIG. 6A indicate electrodes in a second layer.
A collector region is provided by, for example, stacking an n− type semiconductor layer 51b on an n+ type silicon semiconductor substrate 51a. A base region 53, which is a p type impurity region, is provided on the top surface of the n− type semiconductor layer 51b. An emitter region 54 is formed by diffusing n type impurities in a lattice form in the top surface of the base region 53. Thereby, the base region 53 is separated into islands, which are arranged in the emitter region 54 in an alternating manner. Note that, specifically, only a superficial structure of the base region 53 is separated into the islands, and a deep region of the base region 53 that is deeper than the emitter region 54 remains a single continuous region. A transistor formed of one of the separate islands of the base region and a portion of the emitter region surrounding the island will be hereinafter referred to as a cell, and a region in which a large number of cells are arranged will be referred to as an operation region 58.
Each of base electrodes connected to the base regions 53 and emitter electrodes connected to the emitter region 54 has a two-layer structure. The base electrodes in a first layer are island-like first base electrodes 56a and stripe-like first base electrodes 56b, and are in contact with the base region 53 through contact holes CHB formed in a first insulating film 61. The island-like first base electrodes 56a are arranged in one of two regions obtained by dividing the operation region 58 substantially along the center line, and the strip-like first base electrodes 56b are arranged in the other region.
The first emitter electrode 57 is provided in a lattice form in a region between the first base electrodes 56a, 56b, and is in contact with the emitter region 54 through contact holes CHE formed in the first insulating film 61.
A second insulating film 62 is provided on the first base electrodes 56a, 56b, and the first emitter electrode 57. A plate-like second base electrode 66 and a plate-like second emitter electrode 67 constituting the second layer are provided on the second insulating film 62. The second base electrode 66 is in contact with the island-like first base electrodes 56a and one ends of the strip-like first base electrodes 56b via through holes THB formed in the second insulating film 62 (FIG. 6B). The second emitter electrode 67 is in contact with the first emitter electrode 57 via through holes THE formed in the second insulating film 62 (FIG. 6C). The plate-like second base electrode 66 has approximately the same area as the plate-like second emitter electrode 67. Bonding wires (not shown) made of a material such as gold (Au) are connected to the second base electrode 66 and the second emitter electrode 67.
As shown in FIG. 6C, under the second base electrode 66, collector currents flow to the second emitter electrode 67 through the first emitter electrode 57 under the second base electrode 66. The problem here is that long current paths CP2′, CP3′ to the second emitter electrode 67 have a higher resistance than current paths CP1′ under the second emitter electrode 67 because the electrode in the first layer (the first emitter electrode 57) has a smaller thickness than the electrode in the second layer (the second emitter electrode 67).
This causes the problem that most of the collector currents tend to flow through the current paths CP1′ and thus leads to non-uniform current density of the chip. The non-uniform current density increases the risk of thermal runaway, which leads to a problem of reducing the size of ASO. Additionally, the non-uniform current density might prevent some of cells from being activated when the semiconductor device 100 is turned on, which leads to the problem of further increasing resistance components and thus further increasing the non-uniformity of the current density.